Algorithm Development of a Sampled Data Frequency Modulation Demodulator for the Implementation of Software Defined Radios

Thomas Kokumo Yesufu; Abiodun Alani Ogunseye

doi:doi:10.11648/j.cssp.20150404.11

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Algorithm Development of a Sampled Data Frequency Modulation Demodulator for the Implementation of Software Defined Radios

Thomas Kokumo Yesufu, Abiodun Alani Ogunseye

Published in Science Journal of Circuits, Systems and Signal Processing (Volume 4, Issue 4)

Received: 23 July 2015 Accepted: 31 July 2015 Published: 13 August 2015

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Abstract

The study developed and evaluated the performance of an improved algorithm to demodulate sampled data frequency modulation (FM) signals in typical field programmable gate array (FPGA) - based software defined radios (SDR). An algorithm, based on the modification of a standard differentiate-divide FM demodulator was developed. The hardware resources requirement and the input noise suppression ability of the developed algorithm were investigated. The demodulator developed requires a quarter of the hardware resources needed by conventional differentiate-divide FM demodulators. The output signal to noise ratio (SNR) of the developed demodulator is lower than that of the standard differentiate divide-demodulator when the input carrier to noise ratio (CNR) is less than 45 decibels. The SNR plot of the developed demodulator is more linear, compared to that of the original differentiate-divide demodulator. This implies that the developed demodulator can be implemented using smaller sized FPGAs, thus reducing cost and the power dissipated. The small silicon area occupied by the demodulator gives room for instantiation of more demodulators and other signal processing units on the same FPGA chip

Published in	Science Journal of Circuits, Systems and Signal Processing (Volume 4, Issue 4)
DOI	10.11648/j.cssp.20150404.11
Page(s)	23-29
Creative Commons	This is an Open Access article, distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution and reproduction in any medium or format, provided the original work is properly cited.
Copyright	Copyright © The Author(s), 2015. Published by Science Publishing Group

Keywords

Software Defined Radio, FM Demodulator, Differentiate-Divide Demodulator

References

[1]	Cloninger, C., (2003): “Software-Defined Radio comes of Age”, Available online: www.eetimes.com, (Accessed date: 17th March, 2012).
[2]	Di Stefano, A., Fiscelli, G. and Giaconia, C. G. (2006): “An FPGA- Based Software-Defined Radio Platform for the 2.4GHz ISM Band”. Research in Microelectronics and Electronics 2006, Ph.D, pp. 73-76.
[3]	Gustafsson, E. M. I., (2008): “Reconfigurable Analog to Digital Converters for Low Power Wireless Applications”, Doctoral Dissertation. KTH-Royal Institute of Technology, Stockholm, Sweden.
[4]	Hentati, M., Nafkha, A., Leray, P., Nezan, J. and Abid, M., (2012):” Software Defined Radio Equipment: What’s the Best Design Approach to Reduce Power Consumption and Increase Reconfigurability?”, International Journal of Computer Applications, Vol. 45, No. 14, pp. 26-32.
[5]	Le, T. H., (2004):”AM/FM Digital Radio Receiver Implementation in FPGA”, M.Sc Thesis University of Adelaide, Adelaide.
[6]	Lyons, R. G, (2007):” A differentiator With a Difference”, Available online: http://www.dsprelated.com, (Accessed Date: 10th March, 2012).
[7]	Ogunseye, A.A. (2013): Development of a Sampled Data Frequency Modulation (FM) Demodulator for the Implementation of Software Defined Radios, An M.Sc. Thesis submitted to the Department of Electronic and Electrical Engineering, Obafemi Awolowo University, Ile-Ife, Nigeria.
[8]	Rice, M., Padilla, M. and Nelson, B., (2009): “On FM Demodulators in Software Defined Radios Using FPGAs”,IEEE International Conference on Military Communications (MILCOM), pp. 1-7.
[9]	Rudra, A., (2003): “Multichannel, Multiband VHF Software Radio Based Receiver Eliminates R.F Downconversion”, Available online: http://mobiledevdesign.com, (Accessed date: 10th June, 2012).
[10]	Szalchetco, B. and Lewandowski, A., (2013): “A Multichannel Receiver of the Experimental FM Based Passive Radar Using Software Defined Radio Technology”, International Journal of Electronics and Telecommunications, Volume 58, Issue 4, pp. 301–306.
[11]	Tuttlebee, W., (2002): “Software Defined Radio: Enabling Technologies”, West Sussex, Wiley, pp. 6-7.

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Thomas Kokumo Yesufu, Abiodun Alani Ogunseye. (2015). Algorithm Development of a Sampled Data Frequency Modulation Demodulator for the Implementation of Software Defined Radios. Science Journal of Circuits, Systems and Signal Processing, 4(4), 23-29. https://doi.org/10.11648/j.cssp.20150404.11

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ACS Style

Thomas Kokumo Yesufu; Abiodun Alani Ogunseye. Algorithm Development of a Sampled Data Frequency Modulation Demodulator for the Implementation of Software Defined Radios. Sci. J. Circuits Syst. Signal Process. 2015, 4(4), 23-29. doi: 10.11648/j.cssp.20150404.11

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AMA Style

Thomas Kokumo Yesufu, Abiodun Alani Ogunseye. Algorithm Development of a Sampled Data Frequency Modulation Demodulator for the Implementation of Software Defined Radios. Sci J Circuits Syst Signal Process. 2015;4(4):23-29. doi: 10.11648/j.cssp.20150404.11

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@article{10.11648/j.cssp.20150404.11,
  author = {Thomas Kokumo Yesufu and Abiodun Alani Ogunseye},
  title = {Algorithm Development of a Sampled Data Frequency Modulation Demodulator for the Implementation of Software Defined Radios},
  journal = {Science Journal of Circuits, Systems and Signal Processing},
  volume = {4},
  number = {4},
  pages = {23-29},
  doi = {10.11648/j.cssp.20150404.11},
  url = {https://doi.org/10.11648/j.cssp.20150404.11},
  eprint = {https://article.sciencepublishinggroup.com/pdf/10.11648.j.cssp.20150404.11},
  abstract = {The study developed and evaluated the performance of an improved algorithm to demodulate sampled data frequency modulation (FM) signals in typical field programmable gate array (FPGA) - based software defined radios (SDR). An algorithm, based on the modification of a standard differentiate-divide FM demodulator was developed. The hardware resources requirement and the input noise suppression ability of the developed algorithm were investigated. The demodulator developed requires a quarter of the hardware resources needed by conventional differentiate-divide FM demodulators. The output signal to noise ratio (SNR) of the developed demodulator is lower than that of the standard differentiate divide-demodulator when the input carrier to noise ratio (CNR) is less than 45 decibels. The SNR plot of the developed demodulator is more linear, compared to that of the original differentiate-divide demodulator. This implies that the developed demodulator can be implemented using smaller sized FPGAs, thus reducing cost and the power dissipated. The small silicon area occupied by the demodulator gives room for instantiation of more demodulators and other signal processing units on the same FPGA chip},
 year = {2015}
}

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TY  - JOUR
T1  - Algorithm Development of a Sampled Data Frequency Modulation Demodulator for the Implementation of Software Defined Radios
AU  - Thomas Kokumo Yesufu
AU  - Abiodun Alani Ogunseye
Y1  - 2015/08/13
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DO  - 10.11648/j.cssp.20150404.11
T2  - Science Journal of Circuits, Systems and Signal Processing
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AB  - The study developed and evaluated the performance of an improved algorithm to demodulate sampled data frequency modulation (FM) signals in typical field programmable gate array (FPGA) - based software defined radios (SDR). An algorithm, based on the modification of a standard differentiate-divide FM demodulator was developed. The hardware resources requirement and the input noise suppression ability of the developed algorithm were investigated. The demodulator developed requires a quarter of the hardware resources needed by conventional differentiate-divide FM demodulators. The output signal to noise ratio (SNR) of the developed demodulator is lower than that of the standard differentiate divide-demodulator when the input carrier to noise ratio (CNR) is less than 45 decibels. The SNR plot of the developed demodulator is more linear, compared to that of the original differentiate-divide demodulator. This implies that the developed demodulator can be implemented using smaller sized FPGAs, thus reducing cost and the power dissipated. The small silicon area occupied by the demodulator gives room for instantiation of more demodulators and other signal processing units on the same FPGA chip
VL  - 4
IS  - 4
ER  -

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Author Information

Thomas Kokumo Yesufu

Department of Electronic and Electrical Engineering, Obafemi Awolowo University, Ile-Ife, Nigeria
Abiodun Alani Ogunseye

Department of Electrical /Electronics and Computer Engineering, Bells University of Technology, Ota, Nigeria

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Plain Text BibTeX RIS

APA Style

Thomas Kokumo Yesufu, Abiodun Alani Ogunseye. (2015). Algorithm Development of a Sampled Data Frequency Modulation Demodulator for the Implementation of Software Defined Radios. Science Journal of Circuits, Systems and Signal Processing, 4(4), 23-29. https://doi.org/10.11648/j.cssp.20150404.11

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ACS Style

Thomas Kokumo Yesufu; Abiodun Alani Ogunseye. Algorithm Development of a Sampled Data Frequency Modulation Demodulator for the Implementation of Software Defined Radios. Sci. J. Circuits Syst. Signal Process. 2015, 4(4), 23-29. doi: 10.11648/j.cssp.20150404.11

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AMA Style

Thomas Kokumo Yesufu, Abiodun Alani Ogunseye. Algorithm Development of a Sampled Data Frequency Modulation Demodulator for the Implementation of Software Defined Radios. Sci J Circuits Syst Signal Process. 2015;4(4):23-29. doi: 10.11648/j.cssp.20150404.11

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@article{10.11648/j.cssp.20150404.11,
  author = {Thomas Kokumo Yesufu and Abiodun Alani Ogunseye},
  title = {Algorithm Development of a Sampled Data Frequency Modulation Demodulator for the Implementation of Software Defined Radios},
  journal = {Science Journal of Circuits, Systems and Signal Processing},
  volume = {4},
  number = {4},
  pages = {23-29},
  doi = {10.11648/j.cssp.20150404.11},
  url = {https://doi.org/10.11648/j.cssp.20150404.11},
  eprint = {https://article.sciencepublishinggroup.com/pdf/10.11648.j.cssp.20150404.11},
  abstract = {The study developed and evaluated the performance of an improved algorithm to demodulate sampled data frequency modulation (FM) signals in typical field programmable gate array (FPGA) - based software defined radios (SDR). An algorithm, based on the modification of a standard differentiate-divide FM demodulator was developed. The hardware resources requirement and the input noise suppression ability of the developed algorithm were investigated. The demodulator developed requires a quarter of the hardware resources needed by conventional differentiate-divide FM demodulators. The output signal to noise ratio (SNR) of the developed demodulator is lower than that of the standard differentiate divide-demodulator when the input carrier to noise ratio (CNR) is less than 45 decibels. The SNR plot of the developed demodulator is more linear, compared to that of the original differentiate-divide demodulator. This implies that the developed demodulator can be implemented using smaller sized FPGAs, thus reducing cost and the power dissipated. The small silicon area occupied by the demodulator gives room for instantiation of more demodulators and other signal processing units on the same FPGA chip},
 year = {2015}
}

Copy | Download

TY  - JOUR
T1  - Algorithm Development of a Sampled Data Frequency Modulation Demodulator for the Implementation of Software Defined Radios
AU  - Thomas Kokumo Yesufu
AU  - Abiodun Alani Ogunseye
Y1  - 2015/08/13
PY  - 2015
N1  - https://doi.org/10.11648/j.cssp.20150404.11
DO  - 10.11648/j.cssp.20150404.11
T2  - Science Journal of Circuits, Systems and Signal Processing
JF  - Science Journal of Circuits, Systems and Signal Processing
JO  - Science Journal of Circuits, Systems and Signal Processing
SP  - 23
EP  - 29
PB  - Science Publishing Group
SN  - 2326-9073
UR  - https://doi.org/10.11648/j.cssp.20150404.11
AB  - The study developed and evaluated the performance of an improved algorithm to demodulate sampled data frequency modulation (FM) signals in typical field programmable gate array (FPGA) - based software defined radios (SDR). An algorithm, based on the modification of a standard differentiate-divide FM demodulator was developed. The hardware resources requirement and the input noise suppression ability of the developed algorithm were investigated. The demodulator developed requires a quarter of the hardware resources needed by conventional differentiate-divide FM demodulators. The output signal to noise ratio (SNR) of the developed demodulator is lower than that of the standard differentiate divide-demodulator when the input carrier to noise ratio (CNR) is less than 45 decibels. The SNR plot of the developed demodulator is more linear, compared to that of the original differentiate-divide demodulator. This implies that the developed demodulator can be implemented using smaller sized FPGAs, thus reducing cost and the power dissipated. The small silicon area occupied by the demodulator gives room for instantiation of more demodulators and other signal processing units on the same FPGA chip
VL  - 4
IS  - 4
ER  -

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